RegViz: Visualize IRQSTS Bitfield

NXP Semiconductors /MKW41Z4 /ZLL /IRQSTS

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IRQSTS

PI=0, PLL_UNLOCK_IRQ=0, FILTERFAIL_IRQ=0, RXIRQ=0, TXIRQ=0, CRCVALID=0, TSM_IRQ=0, CCA=0, CCAIRQ=0, TMR2MSK=0, TMR1MSK=0, SEQIRQ=0, TMR3MSK=0, RXWTRMRKIRQ=0, TMR4MSK=0, ENH_PKT_STATUS=0, WAKE_IRQ=0

Description

INTERRUPT REQUEST STATUS

Fields

SEQIRQ	Sequencer IRQ 0 (0): A Sequencer Interrupt has not occurred 1 (1): A Sequencer Interrupt has occurred
TXIRQ	TX IRQ 0 (0): A TX Interrupt has not occurred 1 (1): A TX Interrupt has occurred
RXIRQ	RX IRQ 0 (0): A RX Interrupt has not occurred 1 (1): A RX Interrupt has occurred
CCAIRQ	CCA IRQ 0 (0): A CCA Interrupt has not occurred 1 (1): A CCA Interrupt has occurred
RXWTRMRKIRQ	Receive Watermark IRQ 0 (0): A Receive Watermark Interrupt has not occurred 1 (1): A Receive Watermark Interrupt has occurred
FILTERFAIL_IRQ	Filter Fail IRQ 0 (0): A Filter Fail Interrupt has not occurred 1 (1): A Filter Fail Interrupt has occurred
PLL_UNLOCK_IRQ	PLL Unlock IRQ 0 (0): A PLL Unlock Interrupt has not occurred 1 (1): A PLL Unlock Interrupt has occurred
RX_FRM_PEND	RX Frame Pending
WAKE_IRQ	WAKE Interrupt Request 0 (0): A Wake Interrupt has not occurred 1 (1): A Wake Interrupt has occurred
TSM_IRQ	TSM IRQ 0 (0): A TSM Interrupt has not occurred 1 (1): A TSM Interrupt has occurred
ENH_PKT_STATUS	Enhanced Packet Status 0 (0): The last packet received was neither 4e- nor 2015-compliant 1 (1): The last packet received was 4e- or 2015-compliant (RX_FRAME_FILTER register should be queried for additional status bits)
PI	Poll Indication 0 (0): the received packet was not a data request 1 (1): the received packet was a data request, regardless of whether a Source Address table match occurred, or whether Source Address Management is enabled or not
SRCADDR	Source Address Match Status
CCA	CCA Status 0 (0): IDLE 1 (1): BUSY
CRCVALID	CRC Valid Status 0 (0): Rx FCS != calculated CRC (incorrect) 1 (1): Rx FCS = calculated CRC (correct)
TMR1IRQ	Timer 1 IRQ
TMR2IRQ	Timer 2 IRQ
TMR3IRQ	Timer 3 IRQ
TMR4IRQ	Timer 4 IRQ
TMR1MSK	Timer Comperator 1 Interrupt Mask bit 0 (0): allows interrupt when comparator matches event timer count 1 (1): Interrupt generation is disabled, but a TMR1IRQ flag can be set
TMR2MSK	Timer Comperator 2 Interrupt Mask bit 0 (0): allows interrupt when comparator matches event timer count 1 (1): Interrupt generation is disabled, but a TMR2IRQ flag can be set
TMR3MSK	Timer Comperator 3 Interrupt Mask bit 0 (0): allows interrupt when comparator matches event timer count 1 (1): Interrupt generation is disabled, but a TMR3IRQ flag can be set
TMR4MSK	Timer Comperator 4 Interrupt Mask bit 0 (0): allows interrupt when comparator matches event timer count 1 (1): Interrupt generation is disabled, but a TMR4IRQ flag can be set
RX_FRAME_LENGTH	Receive Frame Length

Links

() ()